Improved control of polysilicon emitter interfacial oxide using a UHV-compatible LPCVD cluster tool

An improved method of controlling the interfacial oxide in polysilicon emitter bipolar transistors is described, which uses an Ultra High Vacuum (UHV)-compatible Low Pressure Chemical Vapour Deposition cluster tool. In this method, the interfacial oxide between the polysilicon and single-crystal silicon is controlled using an in-situ hydrogen bake prior to polysilicon deposition. The best results are obtained using a combined RCA clean/100:1 HF thinning/in situ hydrogen prebake at 900/spl deg/C. In this clean, the 14 angstrom oxide layer grown during the RCA clean is thinned during the HF treatment and finally removed completely during the hydrogen prebake. Using this method, a very thin interfacial oxide is produced with an oxygen concentration of 2/spl times/10/sup 19/ cm/sup -3/ at the polysilicon/silicon interface. Transmission Electron Microscopy (TEM) shows that the interfacial oxide is thin enough to facilitate epitaxial realignment of the polysilicon during the emitter drive-in. This correlates with an increase in base current and a decrease in emitter resistance. A specific interface resistivity of 21 /spl Omega/ /spl mu/m/sup 2/ is obtained.