A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation

A SPICE model of oxide-based resistive random access memory (RRAM) for dc and transient behaviors is developed based on the conductive filament evolution model and is implemented in large-scale array simulation. The simulations of one transistor-one resistor RRAM array up to 16 kb with wire resistance (R
_wire
) and capacitance (C
_wire
) indicate that: 1) resistance-capacitance delay during RESET and leakage current during SET have significant impact on write operations; 2) with array size enlarging, the power dissipation increases during RESET but decreases during SET; and 3) the increased R
_wire
and C
_wire
lead to the degradation of high resistance state and the fluctuation of low resistance state, respectively.