Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs

In this paper, the conventional single-stage latched comparator is improved for both high speed and low noise flash ADCs. In the proposed method for high-speed applications, the common mode level of output voltage is preserved unchanged during both amplification and latch operations, to speed up the comparison of small voltage differences. Also, the amplitude of digital control signals is reduced in the modified low noise comparator by using a fully differential structure to remove the concern of digital noise coupling on analog section. Worst-Case simulation results for all corners, using the BSIM3 model of a 0.35μm CMOS process, confirm that a 5mv differential input can be simply detected and recovered to full range values, at 800MS/s and 500MS/s update rate, consuming around 780μW and 650μW in high speed and low noise comparators, respectively. This is equivalent to about 60% improvement in speed of the conventional single-stage comparator. Also, the amplitude of the control signals is reduced to about 18% of full range values, from 3.3v to 0.6v, by using the proposed low noise structure. High speed and low noise comparators can be implemented in 288μm
²
and 480μm
²
active area, respectively.