A high-speed QR decomposition processor for carrier-aggregated LTE-A downlink systems

This paper presents a high-speed QR decomposition (QRD) processor targeting the carrier-aggregated 4×4 Long Term Evolution-Advanced (LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65nm CMOS technology, the processor occupies a core area of 0.77mm
²
and produces 72MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 127 mW.