Power modeling and characterization of Graphene-based logic gates

As a result of CMOS technology approaching its physical limits and of the semiconductor market has started asking for materials that are able to implement new smarter devices, Graphene and composites are emerging as potential replacements for Silicon. Unlike true semiconductors, however, Graphene shows a zero-gap energy band structure that could potentially limit its use in digital applications. Nevertheless, recent works have proven the possibility of implementing electrostatically controlled pn-junctions which serve as a basic primitive for a new class of digital logic gates. These gates naturally behave as a 2-to-1 multiplexer in which the polarity of the input select line can be dynamically reconfigured: the Reconfigurable Graphene MUltipleXer (RG-MUX). Interconnection of multiple RG-MUXs with proper assignments of the inputs signals allow to implement all the basic Boolean logic functions. In this work we investigate the electrical properties of RG-MUXs. More specifically, we introduce a power consumption model that could be used in future design and optimization tools for digital circuits. Characterization data obtained through SPICE-level simulations of a RG-MUX are collected and used to validate the model.