A 1.3 V 1.04 GHz-1.30 GHz CMOS phase-locked loop

A low-voltage and high-frequency phase-locked loop for clock generation has been developed. It consists of a phase detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. In order to make our phase-locked loop operate at a low supply voltage, a new voltage-control resistor is designed to overcome a transistor's threshold voltage for a wide-range control in the voltage-control oscillator. With a high-frequency operation, the adequate loop gain of the phase-locked loop has been effectively addressed to achieve a stable locking process. The low-power and high-frequency circuit design schemes are also presented. The proposed phase-locked loop has been implemented by using the UMC 0.5 u double-poly double-metal CMOS technology with a die size of 200 /spl mu/m/spl times/400 /spl mu/m. The HSPICE simulation results show that the clocks from 1.04 GHz to 1.30 GHz can be generated at a supply voltage of 1.3 V. The jitter of the proposed phase-locked loop at 1.2 GHz is below 4 degrees. Its power consumption is around 5.3 mW. Therefore, our phase-locked loop can be widely used in low-power and high-frequency applications.