A novel parallel architecture for a switched-capacitor bandpass sigma-delta modulator

In this paper, we apply parallelism by 4/spl times/ of analog signal processors to the design of a bandpass sigma-delta modulator. We show that the overall speed of the modulator is increased without increasing the speed requirement of the individual building blocks. Several architectures are considered in terms of their resilience to implementation details such as mismatch and gain errors. A switched capacitor circuit is also presented for the proposed modulator.