A 12.8GS/s time-interleaved SAR ADC with 25GHz 3dB ERBW and 4.6b ENOB

This paper presents a 12.8GS/s 32-way hierarchically time-interleaved SAR ADC with 4.6-bit ENOB in 65nm CMOS. The prototype utilizes multi-stage sampling and a cascode sampler circuit to enable greater than 25GHz 3dB effective resolution bandwidth (ERBW). We further employ a pseudo-differential SAR ADC to save power and area. The core circuit occupies only 0.23 mm
²
and consumes a total of 162mW from dual 1.2V/1.1V supplies.