Design of clock distribution networks in presence of process variations

Tolerance to process-induced skew remains one of the major concerns in the design of large-area and highspeed clock distribution networks. Indeed, despite the availability of some efficient exact-zero skew algorithms that can be applied during circuit design, the clock skew remains an important performance limiting factor after chip manufacturing, and is of increasing concern for sub-micron technologies. This tutorial reviews the importance of the problem, its sources, as well as typical examples of existing solutions. Solutions range from design rule strategies to built-in self-compensation methods.