An accurate compact modelling approach for statistical ageing and reliability

In this paper, we demonstrate a compact modelling approach that allows statistical circuit simulation at arbitrary stages of transistor BTI ageing, using advanced compact model generation techniques implemented in the GSS statistical circuit simulation engine RandomSpice. The methodology links statistical TCAD simulations where different `frozen in time' stages of BTI degradation are described in terms of average trapped charge density and the corresponding statistical compact models, to statistical circuit level simulations where aging is expressed in terms of time. To accomplish this task we employ an ageing model that links the average threshold voltage shift and the corresponding average trapped charge density to the aging time. We also illustrate how this method can be used to study the evolution of the SRAM static noise margin with transistor ageing.