Implications of area-array I/O for row-based placement methodology

We empirically study the implications of area-array I/O for placement methodology. Our work develops a three-axis testbed that examines (1) I/O pad regime (area-array vs. peripheral pad locations), (2) I/O and core placement methodology (variants of alternating vs. simultaneous I/O and core placement approaches), and (3) placement engine (hierarchical quadratic for both core and I/O cells vs. pure min-cut for core cells and assignment for I/O). Experimental data show that the area-array I/O regime is rather more forgiving of bad placement methodologies than the peripheral I/O regime. On the other hand, the wrong methodology can still entail substantial losses in solution quality and efficiency.