Understanding models of substrate behaviour for the routing of high I/O packages

This paper explores two models of substrate wireability and examines the implications of these models in the forecast of the application of future generation integrated circuits and their packages, especially emerging generations of chip scale packages (CSPs). This is in order to clarify our understanding of potential technology bottlenecks. This analysis shows how the demands of future generation high pin density packages, exemplified by the wireability demand of CSPs, drive substrates. The importance of routers for the efficient utilisation of substrates is also quantified by this analysis. This work continues research by the authors to attempt to understand the trends in bare and packaged chip interconnection.