Scaling and performance implications for power supply and other signal routing constraints imposed by I/O pad limitations

More than ever, accurate, high-frequency operation of integrated circuits, with smaller devices buried under an expanding superstructure of interconnect layers, depends upon advancements in packaging interface technology. Specifically, we project that at the 50 nm technology node, upwards of 4000 pads/cm/sup 2/ will be required to attain acceptable on-chip power supply uniformity to assure adequate noise margins and correct dynamic circuit operation. We further show that in the context of such packaging capability, down to the 50 nm node, local on-chip wiring poses no interconnect RC or C/sub L/*L barrier to high frequency chip operation, since the fundamental (local wiring) gate delays are limited only by the available device current per available unit width. These fundamental delays are scaling with the technology nodes, but not as rapidly as the most optimistic clock frequency projections. Scaled trans-chip wiring (clocks, global signals), however, exhibits significant wiring-dominated RC delays that are only partially compensated by new conductor/insulator materials, with poorer scaling than local gate delays to the clock frequency projections. Remedies for these limits must be sought in new system and/or process architectures and/or reduced logic depths.