A reduced complexity EPR4 post-processor

A reduced-complexity Extended Partial Response Class 4 (EPR4) detector implemented as a post-processor following a Partial Response Class 4 (PR4) Viterbi detector is described. Previous work showed that a post-processor architecture eliminates the speed bottleneck associated with an EPR4 Viterbi detector while providing comparable performance. The post-processor uses EPR4 metrics to detect and correct minimum distance EPR4 error-events in the binary sequence at the output of a PR4 Viterbi detector. In the new approach, the complexity is greatly reduced without sacrificing performance by considering only those EPR4 error-events deemed most-likely based on their PR4 metrics.