Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors

The continuous increase of the number of cores in tiled chip-multi-processors (CMP) will prevent traditional electronic networks on chip (NoC) to maintain an acceptable tradeoff between performance and power consumption. Recent advances in silicon-photonics open new opportunities for fast and low-energy on-chip interconnections but specific design and tuning is needed. This paper proposes Olympic, an all-optical NoC architecture using a hierarchical topology made up of replicated and cascaded simple photonic building blocks (rings). Local rings connect tiles within clusters directly and a global ring glues together local ones and enables inter-cluster communications. The all-optical approach allows to achieve a low-energy solution, very important for future embedded CMPs. The cost of these benefits resides mainly in the additional optical-electronic-optical conversions needed for inter-cluster transmissions and in this paper we single out promising design tradeoffs using the PARSEC benchmark suite. We show that a careful design of our Olympic clustered architecture can achieve 65% energy reduction with only 1% slowdown compared to a full 2D mesh, for a 16-core CMP.