An algorithm for mapping non-complete binary trees to cellular architecture FPGAs

With the emergence of deep-submicron fabrication processes, routing is fast surpassing logic as the most important factor in total circuit area and speed. Accordingly, mapping algorithms are needed which can efficiently control critical path length. Our method minimizes critical paths while embedding single-output switching functions to cellular-architecture arrays. We use binary trees to represent functions and target a generic square cell array similar to architectures of Atmel AT6 and Xilinx 6200 FPGAs. We compare our mapping results with other approaches for several MCNC benchmarks. For non-complete trees, longest paths of most circuits are within 2/spl times/ the path lengths of the original trees, and on average 17 to 32 percent better than other approaches.