Exposing Reliability/Performance Tradeoff in Non-Volatile Memories Through Erratic Bits Signature Classification

The erratic bits (EB) phenomenon in nonvolatile memory devices (NVMs) has been evidenced in several technologies as a main reliability detractor. Usually, this issue is handled by repair strategies, which spans from static redundancy to dynamic correction codes. This evidences a tradeoff in a reliability/performance domain that is due to the limitation in the repair resources amount and correction strength. In this paper, we expose this tradeoff in different NVM technologies such as embedded nor Flash and phase-change memory devices through accurate EB testing, signature classification procedure, and chip failure rate estimation.