Oversampling current sample/hold structures for digital CMOS process implementation

The inaccuracies obtained by sampling a dynamic input signal is a major source of error in current-mode circuits. A sampled-data feedback architecture is presented for the design of a high-linearity current sample/hold that uses oversampling to overcome the nonlinearity of internal components. Both system and circuit level considerations are discussed, culminating in the design and implementation of both first- and second-order structures in a 2 /spl mu/m p-well CMOS process. Limited test results show a linearity of up to 69 dB at a sampling rate of 5 MHz. These circuits provide an excellent sampling stage for the realization of a high-resolution current-mode /spl Delta//spl Sigma/ A/D converter in a digital CMOS process.