Characteristics of low-energy BF/sub 2/- or As-implanted layers and their effect on the electrical performance of 0.15-/spl mu/m MOSFET's

Low-energy ion implantation is investigated in detail as a method of fabricating ultrashallow and low resistance source/drain (S/D) extensions for 0.15-/spl mu/m MOSFETs. High-temperature rapid thermal annealing (RTA) is found to be essential for obtaining a shallow junction with low sheet resistance. Significant degradation of carrier activation efficiency and a serious increase in sheet resistance were observed when the acceleration energy was lowered to 10 keV. Only 10% of the implanted atoms were activated by either 1-keV BF/sub 2/or As-implantation. Both p- and n-MOSFETs were fabricated using low-energy (10-20 keV) BF/sub 2/- and As-implantation with RTA. The p- and n-MOSFETs with a 0.15-/spl mu/m gate length showed adequate short-channel characteristics, but their drive current was too low. The analysis of the S/D parasitic resistance shows that the low current drivability is due to the increase in the S/D sheet resistance of extensions for a p-MOSFET and the S/D edge resistance under the gate electrode for an n-MOSFET.