Design-space exploration of an eFPGA soft-core based on Multi-Stages Switching Networks

Embedded FPGAs are becoming appealing IPs to enhance modern SoCs, since technology scaling is enabling reconfigurability at lower area impact. This notwithstanding, to become effective eFPGAs should be highly adaptable to support application-specific optimization, in terms of DSP blocks, technology options and floorplan requirements. For that, in this paper, we analyse a soft-core eFPGA template based on Multi-Stage Switching Network which couples high flexibility with a modular design approach based on the regular replication of few simple switch modules for the programmable routing. Implementation on 65nm technology showed the existence of a significantly wide design space which allows to quickly optimize the device for area, speed and/or leakage power. Results show that depending on architectural and technology options adopted, performance can vary in terms of area (~50%), speed (+/-30%) and leakage (~90%) with respect to a reference design.