A Sub-2 W 39.8–44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS

A 39.8-44.6 Gb/s transmitter and receiver chipset designed in 40 nm CMOS is presented. The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side RX uses a quarter-rate CDR architecture. The TX output shows 0.9 ps
_pp
ISI and 0.2 ps
_rms
RJ at 0.87 W. The RX achieves a jitter tolerance of 0.6 UI
_pp
at 100 MHz and an input sensitivity of 20 mV pp\mathchar"702D diff at 1.05 W. The combined transmitter/receiver equalization enables 44.6 Gb/s data transmission using 2
³¹
-1 PRBS at BER 10
^-12
over a channel with >21 dB loss at Nyquist frequency.