Correlation between hot-carrier-induced interface states and GIDL current increase in n-MOSFET's

Correlation between created interface states and GIDL current increase in n-MOSFET's during hot-carrier stress is quantitatively discussed. A trap-assisted two-step tunneling model is used to relate the increased interface-state density (/spl Delta/D/sub it/) with the shift in GIDL current (/spl Delta/I/sub d/). Results show that under appropriate drain-gate biases, the two-step tunneling is so dominant that /spl Delta/I/sub d/ is insensitive to temperatures up to about 50/spl deg/C. With the help of 2-D device simulation, the locations of the drain region with significant two-step tunneling and the energy levels of the traps involved can be found, with both depending on the drain voltage. From these insights on /spl Delta/D/sub it/, /spl Delta/I/sub d/ and their relation, /spl Delta/D/sub it/ near the midgap can be estimated, with an error less than 10% as compared to the results of charge-pumping measurement on the same transistors. Devices with nitrided gate oxide, different gate-oxide thicknesses and different channel dimensions are also tested to verify the above correlation.