A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The proposed digital LDO with the embedded resistance-locked loop (RLL) controller fabricated in 40nm CMOS process can still correctly regulate the output voltage to 0.4 V even when the input voltage scales down to 0.6V. Besides, maximum load current reaches 200mA and the switching noise suppression can be effectively improved by 77% compared to the state-of-the-art digital LDOs.