A 1.3-mW, 1.6-GHz digital delay-locked loop with two-cycle locking time and dither-free tracking

An all-digital DLL with 2-cycle lock time and 47-mUI
_pp
jitter without dithering is presented. Implemented in 65nm CMOS, the DLL consumes only 1.3-mW at 1.6-GHz and occupies 0.016-mm
²
, making it suitable for low-cost clock deskewing and data alignment circuits in large-scale 3D ICs. A set of custom-designed, serially-connected control registers whose propagation delay is matched to that of the delay stages acquires the initial lock setting by propagating a set signal for a duration equal to the delay error. Subsequently, an adaptive phase-interval detector (APID) that finds the delay interval enclosing the optimal delay value with a minimal number of samples keeps the DLL in lock without causing dithering or sacrificing bandwidth.