A 2.5GHz 5.4mW 1-to-2048 digital clock multiplier using a scrambling TDC

A scrambling TDC is proposed to mitigate dithering jitter accumulation in clock multipliers with low reference frequencies. Fabricated in a 90nm CMOS process, the prototype operates with a 1.25MHz reference clock and generates 160MHz and 2.56GHz output clocks with a long-term absolute jitter of 2.7ps
_rms
and 6.28ps
_rms
, respectively.