93% power reduction by automatic self power gating (ASPG) and multistage inverter for negative resistance (MINR) in 0.7V, 9.2µW, 39MHz crystal oscillator

In order to reduce the power consumption of a crystal oscillator (XO), an automatic self power gating (ASPG) and a multistage inverter for a negative resistance (MINR) are proposed. By combining ASPG and MINR, the measured power of a 39-MHz XO in 40-nm CMOS decreases by 93% from 139μW to 9.2μW, which is the lowest power in the published XO's at 0.7V.