High speed ultra low-voltage differential D Flip-Flop for low-voltage CMOS design

In this paper we present a novel differential CMOS D Flip-Flop based on a high-current pass transistor. We use floating capacitors to obtain a current boost at specific events, i.e clock edges. The Flip-Flop presented may be used in any low voltage digital CMOS systems. The delay is reduced to approximately 12% compared to a conventional sense. amplifier differential Flip-Flop. The simulated data provided is obtained using Cadence and 90nm TSMC CMOS process.