Pipelined R22SDF, R4SDC FFT architecture via folding transformation

A novel method for designing a pipelined parallel architectures for the computation of FFT (Fast Fourier Transform) with the procedure of folding transformation and register minimization techniques is presented. The functionality of designed architecture is verified by simulation in hardware description language VHDL. Further architectures namely R2
²
SDF(Radix2
²
Single path delay feedback), R4SDC (Radix4 Single path Delay Commutator) through folding technique with reduced hardware complexity is proposed. A comparison is made between the earlier and proposed architecture.