Optimal device architecture and hetero-integration scheme for III–V CMOS

Low density-of-states (DOS) of carriers and higher dielectric constants in III–Vs warrants transistor architecture with better electrostatics than conventional bulk FinFETs [1]. Additionally, the integration of III–V FinFETs on 300mm silicon wafers is a key technological challenge due to the large lattice-mismatch between III–Vs and silicon [2]. This paper presents a statistical variability study of III–V and Si FinFETs, from which SOI-FinFET architecture is recommended for III–Vs. The co-integration of InAs-OI NMOS and GaSb-OI PMOS on silicon is proposed for its excellent carrier transport and favorable band-lineup. Such hetero-integration is demonstrated on silicon substrate using rapid-melt-growth technique.