A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

A 14-bit SAR ADC is presented that achieves 73.6 dB SNDR at 80 MSPS while using a 1.2-V-only supply. In order to overcome throughput limitations common to conventional SAR ADCs, several techniques are proposed. First, a flash sub-ADC is utilized to resolve the 5 MSBs quickly prior to SAR sequential decisions of the LSBs. Second, the DAC operation is time-interleaved by a factor of 2, increasing speed while allowing a single comparator to be shared between all DACs. Third, fully on-chip DAC charge redistribution allows the DAC settling time to be improved by more than an order of magnitude compared to conventional techniques. Finally, the ADC is fully self-timed through the use of a replica timer circuit in order to take full advantage of the fast DAC settling and comparator decisions. Despite the increased speed, the ADC consumes only 31.1 mW and occupies a core area of 0.55 mm
²
.