Heterogeneous Three-Layer TSV Chip Stacking Assembly With Moldable Underfill

This paper reports the study of 3-D die stacking of three chips through-silicon-via (TSV) interconnections. Two different reflow approaches were used for the three-die stacked flip-chip assembly: 1) sequential reflow and 2) three-die stacked simultaneous reflow. The effect of the reflow approaches of the stacked die assembly with TSV on die warpage, solder wetting, solder voids, and bonding alignment is addressed in this paper. A simple design of experiment was conducted to understand the effect of bond force on thin die stacked assembly and Pb-free microbumps. Results showed that optimum bond force is important to ensure no die cracks during flip-chip bonding for three-layer stacked die. The selection of flux in terms of flux tackiness, flux for good solder wetting, and minimum solder voids in the flip-chip assembly were also addressed in this paper. Low standoff for microjoint assembly often poses a challenge for underfill dispensing process. The standoff between the microbump joint of the chip-on-chip flip-chip bonding is usually ~15-20 μm. The dispensing space is tight and often with limitations on the area where underfill fluids can be dispensed. Therefore, it is important to evaluate the flowability, bleeding of the underfill, and void formation in the underfill for stacked die assembly. The impact of these various factors on the stacked die assembly is discussed in this paper. The reliability of a pyramidal shape three-layer stacked TSV die package was studied by both experiments and finite-element analysis (FEA). The originally designed microbumps were located peripherally around the edge of the die, which induces a concentrated bending force on the lower die when stacking the upper die. FEA simulation results showed that such bump design induces large stress and deflection in the lower die during die stacking process. A new bump layout design has been optimized with some dummy bumps added on the central area of the die to support bending force induced by die stacking. The new design significantly reduces die stress and deflection. A moldable underfill was then used to encapsulate the three-layer stacked chip on the substrate.