Built in self test architecture for testing SRAM using transient current testing

Semiconductor memories most specifically Static Random Access Memories (SRAMs) are becoming very popular in today's System-On-Chip (SOCs). Memories become more susceptible to faults when the complexity of these memories increase as the technology shrinks. In order to detect these faults, March algorithm has been widely used. This detection of faults in SRAM has been a time consuming process. Hence transient current testing (IDDT) methods are used. This paper implements a transient current testing method to detect faults in Complementary Mosfet (CMOS) SRAM cells. By monitoring a transient current pulse during a write operation or a read operation, faults can be detected. In order to detect the fault a Built in self test (BIST) circuit is developed. Simulations are carried out on a 6T SRAM circuit, to detect the difference in amplitude of the IDDT waveform. Simulations are also carried out on a 4 ∗4 SRAM array to detect the occurrence of fault. The SRAM circuit, array circuit and the sensor circuits are designed in 180nm CMOS technology.