Development of readout ASIC for FPCCD vertex detector at the ILC

We have fabricated two new types of readout ASICs for the FPCCD vertex detector, one with a 0.35 μm CMOS process, the other with 0.25 μm CMOS process and evaluated there performance. By using a finely segmented pixel CCD of 5-by-5 μm
²
called FPCCD for the vertex detector, we intend to achieve high vertex resolution as well as suppress pixel occupancy, which is essential for tracking particles and performing flavor tagging at the ILC. FPCCD imposes several requirements upon the readout ASIC concerning readout speed, noise, readout precision and power consumption. The evaluation results towards these requirements are presented and issues to be resolved are discussed.