Abstract:
Two three-stage fully differential operational amplifiers designed in 40nm digital CMOS technology are presented. The proposed operational amplifiers are designed to be a...Show MoreMetadata
Abstract:
Two three-stage fully differential operational amplifiers designed in 40nm digital CMOS technology are presented. The proposed operational amplifiers are designed to be applied in high speed system on chips (SoCs). The proposed operational amplifiers would find applications in continues time system (CTS) or discrete time system (DTS) according to their own frequency response type, which are discussed and verified by postlayout simulation. Under 1.1V supply voltage and 1kΩ+4pF load, simulation results show that 49dB DC gain, 3.2GHz GBW are achieved with 17mA DC current consumption for both operational amplifiers. The RMS input referred noise integrated from DC to 50MHz is 14.2μV for both operational amplifiers. The fully-symmetric layout pattern minimizes the input offset. Each of the operational amplifiers occupies about 0.011mm2 chip area.
Published in: 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
Date of Conference: 08-10 April 2013
Date Added to IEEE Xplore: 01 July 2013
ISBN Information:
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