A charge-trapping-based technique to design low-voltage BiCMOS logic circuits

New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits' performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-/spl mu/m BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates.