Scalability issue in Ti/HfO bipolar resistive memory with 1T-1R configuration by resistance pinning effect during 1st RESET and its solution

The scalability issue of 1T-1R Ti/HfOx BRM, which is resulted from the interaction between BRM and transistor, is demonstrated. While a sufficiently lower V
_forming
can mitigate the RP, an alternative buffer layer Ta is also proposed to further scale the 1T-1R HfOx based BRM.