Electrical Characterization of GaP-Silicon Interface for Memory and Transistor Applications

Process conditions of gallium phosphide (GaP) metal–organic chemical vapor deposition growth on silicon (Si) are optimized by material characterization. Thorough investigation of GaP-Si interface at this optimized growth condition is carried out by electrical characterization with the perspective of applying this heterostructure system for improving the performance of logic transistors and retention time of capacitorless single-transistor dynamic RAM (1T-DRAM). Fabricated GaP-Si heterojunction diodes exhibit an ON-OFF ratio of
$10^{8}$
with similar reverse current as the ideal device simulation results signify immunity to the existing antiphase domains. Finally, MOSFET devices with GaP source-drain having subthreshold swing of 70 mV/dec and an ON-OFF ratio of
$10^{5}$
are demonstrated.