Strain transfer structure as a mobility booster for fully-depleted SOI MOSFETs at the 10nm node

This paper presents mechanical simulations results of an innovative strain transfer structure. The strain induced by the edge relaxation of a buried SiGe layer is compared to strained SOI (sSOI) wafers for Fully Depleted Silicon-On-Insulator. We studied the influence of different dimensions including the active area and demonstrate a transfer of a tensile stress up to 1.3GPa in the Silicon, corresponding about 80% electron mobility enhancement for logic transistors at the 10nm node.