Advanced gate stack work function optimization and substrate dependent strain interactions on HKMG first stacks for 28nm VLSI ultra low power technologies

Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET I
_D,SAT
= 870μA/μm and PFET I
_D,SAT
= 465μA/μm at I
_OFF
= 1nA/μm and V
_DS
= 1V can be demonstrated by using compressive and tensile contact layers on (100)/<;110> substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.