A 12-bit 8.47-fJ/conversion-step 1-MS/s SAR ADC using capacitor-swapping technique

This paper presents a 12-bit 1-MS/s SAR ADC incorporating a sampling capacitor-swapping technique. The proposed swapping technique effectively removes the capacitor- DAC middle-code transition error, resulting in improved linearity, without needing large capacitor size for good capacitor matching. Moreover, an on-the-fly programmable dynamic comparator is adopted in the design for meeting fast comparison as well as low-noise requirements with small power consumption. The ADC was fabricated in 0.11 μm CMOS. It consumes 16.47 μW at 0.9 V supply. Measured DNL and INL are 0.3 LSB and 0.56 LSB respectively. Measured SNR and SFDR are 67.5 dB and 87 dB respectively. ENOB is measured at 10.92 b, equivalent to a FOM of 8.47 fJ/conversion-step.