Memory efficient programmable processor chip for inverse Haar transform

In this correspondence, a processor chip programmable between N=8 and N=1024 for the unidimensional inverse Haar transform (1-D-IFHT) is presented. The processor uses a low latency data-flow with an architecture that minimizes the internal memory and an adder/subtracter as the only computing element. The control logic has a single and modular structure and can be easily extended to longer transforms. A prototype of the 1-D-IFHT processor has been implemented using a standard-cell design methodology and a 1.0-/spl mu/m CMOS process on a 11.7 mm/sup 2/ die. The maximum data rate is close to 60 MHz.