A cost-efficient high-performance bit-serial architecture for robot inverse dynamics computation

The inverse dynamics problem has remained a computational time bottleneck for the control of robot manipulators. This paper proposes a novel cost-efficient parallel and pipelined bit-serial array architecture for its computation to achieve the bit-serial execution time lower bound of O(⌊c
1
k + c
2
kn⌋), where c
1
and c
2
are specified constants, k is the system word length, and n is the number of manipulator links. The core of the system consists of two arrays of multifunctional bit-serial cells. One of the arrays computes the forward iterations, and the other one evaluates the backward recursions of the Newton-Euler dynamics algorithm. At the current state of technology, the resulting high-performance system may be realized in only two custom very large scale integration (VLSI) chips and a minimum number of first-in-first-out register files. The organization, operation, and performance of the proposed array structure is discussed. In addition, the architecture and functionality of an individual multifunctional bit-serial cell, used as the building block of the array structure, is described.