CoSi/sub 2/ with low diode leakage and low sheet resistance at 0.065 /spl mu/m gate length

This paper presents a comprehensive study of four diode leakage reduction methods, i.e. pre-metal deposition sputter clean, pre-metal deposition amorphization implant, high temperature silicidation, and high temperature metal deposition, for Co salicided junctions and their impact on sub-0.18 /spl mu/m CMOS device performance. The preferred methods are high temperature silicidation and/or high temperature Co deposition, which result in low diode leakage and little device degradation. CoSi/sub 2/ formed by the low diode leakage processes can achieve a mean sheet resistance of /spl sim/6 ohm/sq. on N+ gates with gate lengths down to 0.065 /spl mu/m.