A high-performance 0.1 /spl mu/m CMOS with elevated salicide using novel Si-SEG process

High-performance 0.1 /spl mu/m CMOS devices with elevated salicide film for gate electrode and source/drain (S/D) regions and 80-nm gate side-wall have been demonstrated by a novel silicon selective epitaxial growth (SEG) process. Both junction leakage current and electrical bridging between the gate electrode and S/D regions are suppressed by this high-quality and highly-selective Si-SEG process. The elevated-salicide 0.1-/spl mu/m CMOS devices have high reliability and high drive current, and are suitable for future high-performance logic LSIs.