High-temperature reliability behavior of SSI-flash E/sup 2/PROM devices

The high-temperature (T) reliability of merged-transistor Source Side Injection (SSI) Flash NVM devices is evaluated in terms of endurance and SILC-related disturbs, and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room T, Program/Erase (P/E) cycling at 150/spl deg/C results in an improved endurance due to enhanced charge emission, but also in a reduction of the read-disturb margin. Also, a bake of 72 hrs. at 250/spl deg/C does not cure the generated damage and, therefore, no long-term relief of SILC-related disturb effects is expected at 150/spl deg/C.