Low temperature metal-based cell integration technology for gigabit and embedded DRAMs

An advanced memory cell structure with poly/metal word lines and metal bit lines is proposed. The thermal processes are carefully designed for the metal-based cell to be consistent with narrow gap filling, wet cleaning, planarity, and the contact process. The extremely low temperature process also helps suppress the short channel effect of the MOS transistors. The fully self-aligned contact and via-hole technology provides the minimum memory cell area. This technology is promising for future gigabit DRAMs and embedded DRAMs.