1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS

A phase-dependent gain-transition correlated double-sampling technique is proposed and applied to a 10-bit 75-MS/s pipelined analog-to-digital converter. This reduces the accumulation of predictive error of each multiplying digital-to-analog converter stage due to the finite gain of the operational amplifiers, without the need for additional capacitors and switches at the input. With a 10-MHz sinusoidal input, a prototype fabricated in a 0.13- μm CMOS process has a 56.90 dB signal-to-noise plus distortion ratio (SNDR) and a 64.57 dB spurious-free dynamic range (SFDR) at 75 MS/s. For a 37 MHz input at full sampling rate, the SNDR and SFDR are 55.01 and 60.77 dB, respectively. The IC has an active area of 0.65 mm
²
and consumes 32 mW with a 1.2 V supply.