A fully-integrated Ka-band stacked power amplifier in 45nm CMOS SOI technology

A fully-integrated K
_a
-band power amplifier (PA) designed with 2 stacked Cascode cells is implemented in 45nm CMOS SOI technology. The stack configuration overcomes the low breakdown voltages of scaled transistors and provides an output impedance close to 50 Ω. At 37 GHz, and when biased at 3.6 V, the PA delivers a saturated output power (P
_SAT
) and a -1dB compressed output power (P
_1dB
) of 20.2 dBm and 14.5 dBm, respectively, with a peak PAE of 11.2%. With a higher supply voltage of 4.4 V (1.1 V across each transistor), the P
_SAT
and P
_1dB
increase to 21.4 dBm (140 mW) and 17.5 dBm, respectively. The stack configuration allows the PA to deliver high output power at mm-wave frequencies despite the fact that each transistor is biased under a low drain-source voltage.