The design of a very large high performance gigabit switch with shared buffers

Despite the recent advances of technologies, switch size of the switching architecture imposes the primary implementation constraint. Practical switching dimensions on a single chip are limited to a very small scale. To build a larger dimension, more than one module/chip is interconnected by shuffle pattern. Owing to the trade-offs between the switching dimensions and the switching performance, cells/packets that route through these interconnected modules may experience excessive queuing delay. In this paper, we present a modular design of a very large high performance gigabit switch. The proposed architecture consists of routing sub-networks, group of shared buffer, and delivery sub-networks. The basic building block of a routing sub-network is a Banyan network, while the delivery sub-network is built by an N/spl times/N Banyan network, and recursively followed by /spl rho//sup k/ groups of shared buffers, and /spl rho//sup k/ N//spl rho//sup k//spl times/N//spl rho//sup k/ Banyan networks, where /spl rho/ is the speed-up factor and k is incremented from 1 to [log/sub 2/N/log/sub 2//spl rho/]-1. Owing to its low hardware complexities, and its ease of synchronizing among various components, the proposed architecture is able to achieve very high throughput without sacrificing its overall delay/throughput performance.