A power and area efficient 65 nm CMOS delay line ADC for on-chip voltage sensing

This paper presents a 4-bit windowed delay line ADC implemented in 65 nm CMOS technology for VLSI dynamic voltage scaling power management applications. Good linearity is achieved in the proposed power and area efficient ADC without the use of resistors for compensation. The circuit performance was analyzed theoretically and verified experimentally. The measured DNL is within ±0.25 LSB and INL ±0.15 LSB. It occupies an area of 0.009 mm
²
. With a sampling rate of 4 MHz, the ADC is measured to consume a power of 14 µW with ENOB of 4.1 and voltage sensing range from 0.87 V to 1.32 V.